This invention relates to a circuit for determining the capacity of a cell carried, for example, on an electronic wrist watch, and more particularly to a circuit for successively indicating the remaining capacity of such cell in the form of digital and/or analogue values.
Recently in the field of watches or cameras, a widespread tendency appears toward the use of electronic systems. This tendency probably has resulted from the possibility of easily integrating a great variety of complicated circuits in a square semiconductor substrate, each side of which measures only a few millimeters.
A watch or camera comprising intricate integrated electronic circuits naturally has to be supplied with a power source. Since the watch or camera is portable, a primary cell such as a silver oxide type has come into general use. Application of the primary cell to the portable watch or camera necessarily involves the exchange of power cells. Accordingly, the user of such watch or camera must have the primary cell used therewith periodically replaced by a fresh one according to the consumed capacity of the cell or the length of time for which the cell has been used. Consequently, the manufacture of, for example, a portable watch incorporates an abnormal voltage detector, an example of which is shown in FIG. 1, for the easy check of the voltage limit of the primary cell.
Referring to FIG. 1, the prior art cell capacity detector comprises a switch (2), a light-emitting diode (3) and current control resistor (4) connected in series relative to the primary cell (1). Where the light-emitting diode (3) sends forth a light at the short-circuiting of the switch (2), then the primary cell (1) is taken to have a normal level of voltage. Conversely, where the light-emitting diode (3) fails to be lighted at the short-circuiting of the switch (2), then the primary cell (1) is regarded as having an insufficient level of voltage. Such a cell must be replaced by a fresh one.
Referring to the prior art cell capacity detector of FIG. 1, the light-emitting diode (3) has a voltage (V)-current (I) curve (5) (FIG. 2). The current control resistor (4) and load line (6) have such a relationship as allows for the flow of diode current (I.sub.LED) indicated at a junction (7) (FIG. 2). The curve diagram of FIG. 2 shows that where a power source voltage (.vertline.V.sub.SS .vertline.) is higher than the forward voltage (V.sub.F) of the light-emitting diode (3), then a sufficiently large current (I.sub.D) runs through said light-emitting diode (3) to cause it to send forth a light; and conversely where the power source voltage (.vertline.V.sub.SS .vertline.) is lower than the forward voltage (V.sub.F) of the light-emitting diode (3), then said diode (3) fails to be lighted, indicating that the power source voltage (.vertline.V.sub.SS .vertline.) has fallen.
As seen from FIG. 3, the cell capacity detector may be formed of a CMOS inverter (10), consisting of a P channel transistor (8), and an N channel transistor (9), and a bias circuit (13), formed of a bias resistor (11) and a bias N channel transistor (12).
With the cell capacity detector of FIG. 3, the CMOS inverter (10) has a specific threshold voltage. Now let it be assumed that the threshold of inverter (10) is preset to distinguish between the normal and abnormal voltages with the value of said threshold voltage taken to correspond to the output voltage of the primary cell (1). The gate of, for example, the bias N channel transistor (12) is connected to one power source (V.sub.DD). Consequently in the bias circuit (13), connected to the P channel transistor (8) and N channel transistor (9) constituting the inverter (10), the voltage (V.sub.GS) of the gate of said bias N channel transistor (12) successively changes in accordance with the attenuation of the capacity of the primary cell (1), which corresponds to the attenuation of the voltage impressed between the power sources V.sub.DD and V.sub.SS. Resistance between the source and drain regions of the bias N channel transistor (12) varies with the above-mentioned gate voltage (V.sub.GS), thereby ensuring the automatic change of the bias voltage of the inverter (10).
Where, with the cell capacity detector of FIG. 3, the primary cell (1) has a normal level of voltage, then the resistance occurring between the source and drain regions of the bias N channel transistor (12), in cooperation with bias resistor (11), generates at point A (the input terminal of the inverter (10)) a voltage which renders the N channel transistor (9) non-conducting and the P channel transistor (8) conducting. As a result, a normal voltage signal denoting the voltage level of the power source V.sub.DD is sent forth from an output terminal (14).
Where the voltage of the primary cell (1) falls to an abnormally low level, then the resistance appearing between the source and drain regions of the bias N channel transistor (12) increases because the voltage impressed on the gate of said transistor (12) is attenuated to a low level. Therefore, the bias voltage impressed at point A renders the P channel transistor (8) nonconducting and the N channel transistor (9) conducting. Thus, a signal denoting the voltage level of the power source V.sub.SS is produced from the output terminal (14) to indicate that the voltage of the primary cell (1) has fallen to an abnormally low level.
The curve diagram of FIG. 4 is furnished for easy understanding of the operation of the bias circuit (13). FIG. 4 indicates a typical V.sub.DS -I.sub.D curve, where the gate voltage V.sub.GS of the N channel transistor (12) is varied. V.sub.DS represents the source-drain voltage of the transistor (12), and I.sub.D denotes the drain current thereof. The straight line (l) denotes a load line resulting from a load resistor (11) and shows that actual power source voltage V.sub.DS is produced at the junctions between said straight line (l) and the curves. Now let it be assumed that the threshold voltage of the inverter (10) is set at 0.7 volt (in FIG. 3, voltage V.sub.D impressed across both ends of the bias resistor (11) is taken to be 0.7 V); and the cell capacity detector circuit is supplied with a power source voltage of 1.40 volts. This means that the gate of the transistor (12) has been impressed with a voltage of .vertline.V.sub.GS .vertline.=1.40.
If the fall of the voltage .vertline.V.sub.GS .vertline. to a lower level than 1.40 volts is taken to denote the occurrence of abnormal voltage, and it is desired that the inverter (10) change states at the occurrence of said abnormally low voltage, then the load resistor (11) should be adjusted to provide a voltage of .vertline.V.sub.DS .vertline.=.vertline.V.sub.SS .vertline.-.vertline.V.sub.D .vertline.=1.40-0.7=0.7 volt in view of the relationship .vertline.V.sub.SS .vertline.=.vertline.V.sub.D .vertline.+.vertline.V.sub.DS .vertline.. Consequently, said adjustment should be made at point P.
Now let it be assumed that with the bias circuit in which the voltage has been adjusted as described above, the power source voltage has a normal level of, for example, 1.50 volts. Then junction R between the curve representing .vertline.V.sub.GS .vertline.=1.50 and load line (l') set in parallel with load line (l) can be supplied with a voltage of 0.55 volt. Therefore, the voltage V.sub.D impressed across both ends of the bias resistor (11) is set at 1.50-0.55=0.95 volt. As a result, the gate (G) of the inverter (10) is impressed with a voltage of -0.95 volt, and a signal denoting a normal voltage (V.sub.DD) is sent forth from the output terminal (14) of the inverter (10). Conversely, where the gate voltage V.sub.GS of the inverter (10) indicates .vertline.V.sub.GS .vertline..apprxeq.1.30, then voltage V.sub.DS is set at 0.8 volt, and consequently voltage V.sub.D shows a level of 1.30-0.8=0.5. As a result, the N channel transistor (9) is rendered conducting, and a signal having voltage (V.sub.SS), which denotes the abnormal condition of the capacity of the primary cell (1), is produced from the output terminal (14) of the inverter (10).
However, the known cell voltage detectors respectively arranged as shown in FIGS. 1 and 3 have the drawback that the user of, for example, a portable watch is only informed of the normal or abnormal level of the voltage of a cell used with the watch.
In other words, the voltage detector of the above-mentioned type only suddenly informs the user of, for example, a portable watch that the voltage of a cell used therewith has dropped to a lower level than required. Where the user notices such event in the surroundings in which the cell can not be immediately replaced, for example, during a trip or mounting climbing, he finds great difficulties in coping with such situation.
The conventional cell voltage detector does not show how much the capacity of a cell used with, for example, a portable watch has been consumed. Even where 90% and 70% of the cell capacity have been used up, the conventional cell voltage detector indicates this as normal. When the conventional voltage detector displays the abnormal voltage drop of a cell used with a portable watch, then the depleted cell must be immediately replaced. Otherwise, the watch would be stopped.